a. Technical Field
The instant disclosure relates generally to power electronics systems, and more particularly to a gate drive circuit for a power electronics system that includes a plurality of semiconductor switches connected in a paralleled arrangement.
b. Background
This background description is set forth below for the purpose of providing context only. Therefore, any aspects of this background description, to the extent that it does not otherwise qualify as prior art, is neither expressly nor impliedly admitted as prior art against the instant disclosure.
In a power electronics circuit, a high-current power capability can be provided by electrically connecting a plurality of semiconductor switches in a paralleled arrangement so as to permit the undertaking of the load current together. Switches such as Si MOSFETs or GaN high electron mobility transistor (HEMTs) devices can be used in such a paralleled arrangement because they have a much lower conduction resistance compared to a single switch, which will reduce the conduction loss to thereby increase the overall system efficiency.
To avoid a current imbalance in both dynamic and steady states, identical gate-drive resistance and capacitance can be given to each switch in the parallel arrangement. In other words, it is typical to deploy the same gate drive circuit for each switch in a paralleled switch arrangement. However, there can be differences among the multiple switches in this arrangement, e.g., due to the circuit layout, one switch might be physically closer than another switch to a gate-drive chip that is provided for generating a gate drive signal to turn the switches on and off. These differences can cause problems in the operation of the paralleled switch circuit.
The switch that is physically closer to the gate-drive chip (i.e., the near switch) will have a relatively smaller loop inductance, while the switch or switches that are physically farther away from (i.e., the far switch) will have a longer gate-loop length resulting in a larger loop inductance. In a fast switching application, such as a paralleled switch arrangement that includes, for example, GaN HEMTs devices, the differences in the gate loop inductance can cause the switches to turn on and off at different speeds, as well as possibly cause an oscillation of the gate voltage and/or mis-trigger one or more of the switches.
For example, FIG. 3 shows respective timing diagrams of a gate-source voltage (Vgs), a drain-source current (Ids), and a drain-source voltage (Vds) for both a near switch and a far switch. For illustration purposes, the near switch is assumed to have an associated gate-drive loop inductance of about 1 nH and the far switch is assumed to have an associated gate-drive loop inductance of about 2 nH. Additionally, assume that both the near and far switches have the same gate resistance. In the top timing diagram, trace 300 represents the far switch and trace 302 represents the near switch.
When the gate drive signal (from the gate drive chip) transitions from an on state to an off state, the above-mentioned differences in the gate loop inductance cause an oscillation of the gate voltage, which in turn affects the switch voltage and current. In the middle timing diagram, trace 304 represents the far switch and trace 302 represents the near switch. As shown, the current Ids also shows oscillation, as does the voltage Vds trace 308 (far switch). Such oscillations can cause mis-triggering of the switches, which in turn can result in unexpected and/or undesired operation of the system (e.g., bridge shoot-through or damage to the gate).
The foregoing discussion is intended only to illustrate the present field and should not be taken as a disavowal of claim scope.